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| Click to see this datasheet in Simplified Chinese! FSA2467 -- 0.4 Low-Voltage Dual DPDT Analog Switch April 2008 FSA2467 0.4 Low-Voltage Dual DPDT Analog Switch Features Typical 0.4 On Resistance (RON) for +2.7V supply Features Less then12A ICCT Current when Sn Input is Lower than VCC 0.25 Maximum RON Flatness for +2.7V Supply 3x3mm 16-Lead Pb-Free MLP Package 1.8x2.6mm 16-Lead Pb-Free UMLP Package Broad VCC Operating Range Low THD (0.02% Typical for 32 Load) Description The FSA2467 is a dual Double-Pole, Double-Throw (DPDT) analog switch. The FSA2467 operates from a single 1.65V to 4.3V supply. The FSA2467 features an ultra-low on resistance of 0.4 at a +2.7V supply and 25C. This device is fabricated with sub-micron CMOS technology to achieve fast switching speeds and is designed for break-before-make operation. FSA2467 features very low quiescent current even when the control voltage is lower than the VCC supply. This feature allows mobile handset applications direct interface with baseband processor general-purpose I/Os. Applications Cell Phone PDA Portable Media Player Ordering Information Part Number FSA2467MPX FSA2467UMX Package Description 16-lead Molded Leadless Package (MLP), JEDEC MO-220, 3x3mm Square 16-lead Ultrathin Molded Leadless Package (UMLP), 1.8x2.6mm All packages are lead free per JEDEC: J-STD-020B standard. Application Diagram Figure 1. Application Diagram (c) 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com FSA2467 -- 0.4 Low-Voltage Dual DPDT Analog Switch Pin Assignments Figure 2. Pin Assignments Truth Table Control Inputs LOW HIGH Pin Descriptions Function nB0 Connected to nA nB1 Connected to nA Name nAnB0nB1 nS Function Data Ports Control Input Analog Symbol Figure 3. Analog Symbol (c) 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 2 FSA2467 -- 0.4 Low-Voltage Dual DPDT Analog Switch Absolute Maximum Ratings Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VS VIN IIK ISW ISWPEAK TSTG TJ TL ESD Supply Voltage Switch Voltage Input Voltage Parameter Min. -0.5 -0.5 -0.5 -50 Max. 4.6 VCC+0.3 4.6 350 500 Unit V V V mA mA mA C C C kV Input Diode Current Switch Current Peak Switch Current (Pulsed at 1ms duration, <10% Duty Cycle) Storage Temperature Range Junction Temperature Lead Temperature, Soldering 10 Seconds Human Body Model -65 +150 +150 +260 5.5 Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC VIN VIN TA Note 1. Supply Voltage Parameter Control Input Voltage(1) Switch Input Voltage Operating Temperature Min. 1.65 0 0 -40 Max. 4.30 VCC VCC +85 Unit V V V C Unused inputs must be held HIGH or LOW. They may not float. (c) 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 3 FSA2467 -- 0.4 Low-Voltage Dual DPDT Analog Switch DC Electrical Characteristics Typical values are at 25C unless otherwise specified. TA = +25C Symbol Parameter Conditions VCC (V) Min. 4.3 VIH Input Voltage High 2.7 to 3.6 2.3 to 2.7 1.65 to 1.95 4.3 VIL Input Voltage Low 2.7 to 3.6 2.3 to 2.7 1.65 to 1.95 IIN Control Input Leakage VIN=0V to VCC nA=0.3V, VCC-0.3V nB0 or nB1=0.3V, VCC-0.3V or floating nA=0.3V,VCC0.3V nB0 or nB1=0.3V, VCC-0.3V or floating IOUT=100mA nB0 or nB1=0V,0.8V, 1.8V,2.7V IOUT=100mA, nB0 or 1=0V,0.7V, 1.2V, 2.3V IOUT=100mA, nB0 or nB1=1.0V On Resistance Matching (3) Between Channels IOUT=100mA, nB0 or nB1=0.8V IOUT=100mA, nB0 or nB1=0.7V IOUT=100mA, B0 or nB1=0V to VCC VIN=0V to VCC IOUT=0V VIN=1.8V VIN=2.6V 1.95 to 4.30 -10.0 10.0 -50.0 50.0 nA 1.95 to 4.30 -10.0 10.0 -50.0 50.0 nA 1.65 to 4.30 -0.5 TA = -40 to +85C Min 1.4 1.3 1.1 0.9 0.7 0.5 0.4 0.4 0.5 Units Typ. Max. Max. V V A INO(OFF) INC(OFF) Off Leakage Current of Port nB0 and nB1 IA(ON) On Leakage Current of Port A 4.3 2.7 0.4 0.4 0.6 0.6 RON Switch On Resistance (2) 2.3 0.55 0.95 1.8 2.7 2.3 2.7 2.3 4.3 4.3 4.3 0.8 0.04 0.03 2.0 0.10 0.10 0.25 0.3 nA A RON RFLAT(ON) ICC ICCT On Resistance Flatness (4) Quiescent Supply Current Increase in ICC Current per Control Voltage -100 7.0 3.0 100 12.0 6.0 -500 500 15.0 7.0 Notes: 2. On resistance is determined by the voltage drop between A and B pins at the indicated current through the switch. 3. RON=RON max - RON min measured at identical Vcc, temperature and voltage. 4. Flatness is defined as the difference between the maximum and minimum value of on resistance over the specified range of conditions. (c) 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 4 FSA2467 -- 0.4 Low-Voltage Dual DPDT Analog Switch AC Electrical Characteristics Typical values are at 25C unless otherwise specified. Symbol Parameter Conditions nB0 or nB1=1.5V tON Turn-On Time RL=50, CL=35pF VCC Min. 3.6 to 4.3 2.7 to 3.6 2.3 to 2.7 TA = +25C Typ. Max. 50 65 80 32 42 52 12 15 20 15 10 8 -75 -75 -75 -75 -75 -75 85 0.02 0.02 0.02 TA = -40 to +85C Min. Max. 60 75 90 40 50 60 Units Figure ns Figure 7 nB0 or nB1=1.5V tOFF Turn-Off Time RL=50, CL=35pF 3.6 to 4.3 2.7 to 3.6 2.3 to 2.7 ns Figure 7 nB0 or nB1=1.5V tBBM Break-BeforeMake Time RL=50, CL=35pF CL=100pF, VGEN=0V, RGEN=0 Q Charge Injection CL=100pF, VGEN=0V, RGEN=0 CL=100pF, VGEN=0V, RGEN=0 f=100KHz, RL=50,CL=5pF 3.6 to 4.3 2.7 to 3.6 2.3 to 2.7 3.6 to 4.3 2.7 to 3.6 2.3 to 2.7 3.6 to 4.3 ns Figure 8 pC Figure 10 OIRR Off Isolation 2.7 to 3.6 2.3 to 2.7 dB Figure 9 Xtalk Crosstalk f=100KHz, RL=50, CL=5pF RL=50 RL=32, VIN=2VPP, f=20 to 20kHZ 3.6 to 4.3 2.7 to 3.6 2.3 to 2.7 dB Figure 9 Figure 12 BW -3dB Bandwidth 2.3 to 4.3 3.6 to 4.3 2.7 to 3.6 2.3. to 2.7 MHZ THD Total Harmonic Distortion RL=32, VIN=2VPP, f=20 to 20kHZ RL=32, VIN=2VPP, f=20 to 20kHZ % Figure 13 Capacitance Symbol CIN COFF CON Parameter Control Pin Input Capacitance B Port Off Capacitance A Port On Capacitance Conditions f=1MHZ f=1MHZ f=1MHZ VCC 0 3.3 3.3 TA = +25C Typical 1.5 32 118 Units pF pF pF Figure Figure 7 Figure 7 Figure 7 (c) 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 5 FSA2467 -- 0.4 Low-Voltage Dual DPDT Analog Switch Typical Applications Figure 4. RON at 2.7V VCC Figure 5. RON at 2.3V VCC Figure 6. RON at 1.8V VCC (c) 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 6 FSA2467 -- 0.4 Low-Voltage Dual DPDT Analog Switch AC Loadings and Waveforms Figure 7. Turn-On / Turn-Off Timing Figure 8. Break-Before-Make Timing Figure 9. Off Isolation and Crosstalk (c) 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 7 FSA2467 -- 0.4 Low-Voltage Dual DPDT Analog Switch AC Loadings and Waveforms (Continued) Figure 10. Charge Injection Figure 11. On / Off Capacitance Measurement Setup Figure 12. Bandwidth Figure 13. Harmonic Distortion (c) 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 8 FSA2467 -- 0.4 Low-Voltage Dual DPDT Analog Switch Tape and Reel Specifications Tape Format for MLP Package Designator Tape Section Leader (Start End) MPX Carrier Trailer (Hub End) Number Cavities 125 (typical) 2500/3000 75 (typical) Cavity Status Empty Filled Empty Cover Tape Status Sealed Sealed Sealed Tape Size (12mm) A 13.000 (330.00) B 0.059 (1.50) C 0.512 (13.00) D 0.795 (20.20) N 7.008 (178.00) W1 0.488 (12.40) W2 0.724 (18.40) (c) 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 9 FSA2467 -- 0.4 Low-Voltage Dual DPDT Analog Switch Package Dimensions Figure 14. 16-Lead, Molded Leadless Package (MLP), JEDEC MO-220 3x3mm Square Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c) 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 10 FSA2467 -- 0.4 Low-Voltage Dual DPDT Analog Switch Package Dimensions 0.10 C 2.100 2X 1.80 A B 0.663 0.563 15X 1 PIN #1 IDENT 2.60 2.900 0.400 0.10 C 2X TOP VIEW 0.55 MAX. 0.10 C 0.152 SEATING PLANE 0.225 16X RECOMMENDED LAND PATTERN 0.08 C 0.050 C SIDE VIEW TERMINAL SHAPE VARIANTS 0.40 0.60 5 9 0.15 0.25 0.40 0.100 0.100 15X 0.15 0.25 NON-PIN 1 0.30 15X 0.50 PIN 1 Supplier 1 1 16 13 ALL TERMINALS 0.10 C A B 0.05 C 0.15 0.25 PIN 1 0.30 0.50 15X 0.25 NON-PIN 1 0.15 0.30 15X 0.50 Supplier 2 BOTTOM VIEW A. THIS PACKAGE IS NOT CURRENTLY REGISTERED WITH ANY STANDARDS COMMITTEE B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. TERMINAL SHAPE MAY VARY ACCORDING TO PACKAGE SUPPLIER, SEE TERMINAL SHAPE VARIANTS E. LAND PATTERN IS A MINIMAL TOE DESIGN F. DRAWING FILE NAME : UMLP16AREV3 Figure 15. 16-Lead, Ultrathin Molded Leadless Package (UMLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ (c) 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 11 FSA2467 -- 0.4 Low-Voltage Dual DPDT Analog Switch (c) 2005 Fairchild Semiconductor Corporation FSA2467 Rev. 1.0.5 www.fairchildsemi.com 12 |
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